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Hello, Thank You! And thank you so much for getting back to me and with so much info ! Also Thank you for adding the IMPLY/NIMPLY levels. (117 complete !)
p.s. Latches made from AND/OR/NOT in the sim don't work since I'm guessing all signals reach their destination at the exact same time but for whatever reason, NAND latches seem to work reliably.

p.p.s Would it interest you to see a ZIP of the solutions to all my levels ?

And would it be possible to get around the high impedance issue by instead, adding a second type of wire that acts differently for specific components ?

@macerator420,

Yes, you are correct, the simulator assumes zero travel time for signals within components, including wires. The simulator still has to adjudicate signal changes in an ordered manner, so depending on the specifics of the latch or flip-flop your mileage will vary on how well it works.