can you make the delay of a clock slower?
Viewing post in Digital Logic Sim (old version) comments
Yes, you can.
Just make this scheme.
[CLOCK-makes clock signals, if input is "1"]
[ON-constant "1" output]
[GATE-lets inputs signals to output, if POWER input is "1"]
[INC-increases binary input by 1]
Register was made in dev's second video.
In results, we have 8 outputs, which switches on with different frequencies. Choose any you want.